Sequential Circuits — Latches, Flip-Flops, Counters
398 words
2 min read
Visual companion
Python
Type and operator map
Python Week 1: the first filter for runtime behavior
View
Revision summary
What this note is really saying
Short form
# Sequential Circuits — Latches, Flip-Flops, Counters ## 🎯 Learning Objectives - Differentiate between latch and flip-flop - Design circuits using SR, D, JK, and T flip-flops - Build synchronous counters and shift registers - Analyze timing diagrams of sequential circuits * * * ## 1. Latches vs Flip-Flops Aspect La...
Sequential Circuits — Latches, Flip-Flops, Counters
🎯 Learning Objectives
- Differentiate between latch and flip-flop
- Design circuits using SR, D, JK, and T flip-flops
- Build synchronous counters and shift registers
- Analyze timing diagrams of sequential circuits
1. Latches vs Flip-Flops
| Aspect | Latch | Flip-Flop |
|---|---|---|
| Trigger | Level-sensitive | Edge-triggered |
| Transparency | Transparent when enabled | Output only at edge |
| Usage | Timing elements, registers | Synchronous design |
| Complexity | Simple | More complex |
1.1 SR Latch (NOR implementation)
(Diagram)
| S | R | Q | ¬Q | State |
|---|---|---|---|---|
| 0 | 0 | Q | ¬Q | Hold |
| 0 | 1 | 0 | 1 | Reset |
| 1 | 0 | 1 | 0 | Set |
| 1 | 1 | — | — | Invalid |
1.2 D Flip-Flop (Edge-Triggered)
(Diagram)
| CLK ↑ | D | Q |
|---|---|---|
| Rising | 0 | 0 |
| Rising | 1 | 1 |
| Other | — | Hold |
Characteristic equation:
2. Flip-Flop Types
| Type | Input(s) | Equation | Application |
|---|---|---|---|
| SR | S, R | Basic storage | |
| D | D | Registers, latches | |
| JK | J, K | Counters | |
| T | T | Toggle, counters |
3. Counters
3.1 3-Bit Synchronous Up Counter
(Diagram)
| Clock | Q₂ | Q₁ | Q₀ | Value |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 1 |
| 2 | 0 | 1 | 0 | 2 |
| 3 | 0 | 1 | 1 | 3 |
| 4 | 1 | 0 | 0 | 4 |
| 5 | 1 | 0 | 1 | 5 |
| 6 | 1 | 1 | 0 | 6 |
| 7 | 1 | 1 | 1 | 7 |
| 8 | 0 | 0 | 0 | 0 |
4. 📝 Practice Questions
Q1: What is the difference between a latch and a flip-flop?Answer: A latch is level-sensitive (transparent while clock is high/low). A flip-flop is edge-triggered (samples input only at rising/falling edge). Flip-flops are preferred in synchronous designs because they eliminate transparency windows. Q2: Design a 4-bit synchronous down counter using T flip-flops.Answer: Same structure as up counter but use Q' outputs to drive T inputs, or use D flip-flops with Q_next = Q - 1 logic. Q3: How many flip-flops are needed for a counter that counts to 100?Answer: Need to count 0-99 (100 states). Need ceil(log₂(100)) = 7 flip-flops (128 states, 28 unused). Q4: What happens when both S and R are 1 in an SR latch?Answer: This is an invalid state. Both outputs Q and ¬Q become 0, violating the complement relationship. When S and R return to 0, the state is indeterminate (depends on which gate responds faster). This race condition is why SR latches are avoided in many designs. Q5: Convert a D flip-flop to a T flip-flop.Answer: Connect D = Q ⊕ T. When T=0: D=Q (hold). When T=1: D=¬Q (toggle). Adding an XOR gate between T and Q drives the D input.
5. 🔗 Cross-References
- Week 2 - Combinational Circuits: Flip-flops add state to logic
- Week 4 - Counters & Registers: More complex sequential blocks
- Week 6 - Processor Design: Registers in CPU Join Discord PreviousCombinational CircuitsNextCounters & Registers