Counters, Registers, and Shift Registers
579 words
3 min read
Visual companion
Python
Type and operator map
Python Week 1: the first filter for runtime behavior
View
Revision summary
What this note is really saying
Short form
# Counters, Registers, and Shift Registers ## 🎯 Learning Objectives - Design synchronous and asynchronous counters - Implement registers using D flip-flops - Design shift registers for serial/parallel conversion - Analyze counter timing and propagation delays * * * ## 1. Registers ### 1.1 4-bit Register using D Fli...
Counters, Registers, and Shift Registers
🎯 Learning Objectives
- Design synchronous and asynchronous counters
- Implement registers using D flip-flops
- Design shift registers for serial/parallel conversion
- Analyze counter timing and propagation delays
1. Registers
1.1 4-bit Register using D Flip-Flops
(Diagram)
Operation: On clock edge, Qᵢ = Dᵢ for all bits simultaneously (parallel load).
2. Shift Registers
2.1 Serial-in, Parallel-out (SIPO)
(Diagram)
Tracing: Input 1011 (MSB first):
| Clock | DIN | Q0 | Q1 | Q2 | Q3 |
|---|---|---|---|---|---|
| 0 | — | 0 | 0 | 0 | 0 |
| 1 | 1 | 1 | 0 | 0 | 0 |
| 2 | 0 | 0 | 1 | 0 | 0 |
| 3 | 1 | 1 | 0 | 1 | 0 |
| 4 | 1 | 1 | 1 | 0 | 1 |
After 4 clocks, Q3Q2Q1Q0 = 1011 (parallel output).
3. Counters
3.1 Synchronous Counter
All flip-flops clocked simultaneously. Faster but more complex logic.
3-bit synchronous binary counter:
| State | Q2 | Q1 | Q0 |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 |
| 2 | 0 | 1 | 0 |
| 3 | 0 | 1 | 1 |
| 4 | 1 | 0 | 0 |
| 5 | 1 | 0 | 1 |
| 6 | 1 | 1 | 0 |
| 7 | 1 | 1 | 1 |
Logic: Q0_toggle always; Q1_toggle when Q0=1; Q2_toggle when Q0=Q1=1.
3.2 Asynchronous (Ripple) Counter
Each FF clocks the next. Simple but slower (propagation delay accumulates).
4-bit ripple counter:
- Clock → FFA (LSB)
- FFA output → FFB clock
- FFB output → FFC clock
- FFC output → FFD clock Delay: 4 × propagation delay per FF. For 4 FF at 10ns each = 40ns. Max frequency = 1/(40ns) = 25 MHz.
3.3 Comparison
| Feature | Synchronous | Asynchronous |
|---|---|---|
| Speed | Fast (limited by 1 FF + logic) | Slow (n × FF delay) |
| Complexity | Higher (more gates) | Lower |
| Glitches | No | Yes (ripple effect) |
| Power | Higher (all clocked) | Lower |
| Use case | High-speed, precise | Low-power, simple |
4. Applications
| Component | Application |
|---|---|
| Register | CPU registers, data storage |
| Shift register | Serial communication (UART), LED matrix |
| Synchronous counter | Program counter, timer |
| Asynchronous counter | Frequency divider, low-power counter |
| Ring counter | Sequence generator, traffic light control |
5. Common Pitfalls
Pitfall: Propagation Delay in Ripple Counters
The mistake: Clocking a ripple counter too fast, causing invalid intermediate states.
Correct approach: Max clock frequency = 1/(n × t_pd). For n=8-bit counter, t_pd=10ns: max = 1/(80ns) = 12.5 MHz.
6. Key Concepts Reference
| Concept | Description |
|---|---|
| Register | Set of flip-flops storing n bits |
| Shift register | Serial/parallel data conversion |
| Synchronous counter | All FFs clocked together |
| Asynchronous counter | FFs clocked sequentially (ripple) |
| Modulus | Number of states in counter |
| Ring counter | Shift register with feedback |
7. 📝 Practice Questions
Q1: Design a mod-6 synchronous counter (states 0→1→2→3→4→5→0).Answer: Use 3 FFs (need 2³ ≥ 6 states). Toggle conditions:
- Q0: toggle always
- Q1: toggle when Q0=1 AND NOT (Q2=1 AND Q1=0 AND Q0=1) [skip state 6]
- Q2: toggle when Q0=Q1=1 AND NOT (Q2=1 AND Q1=0 AND Q0=0) [skip state 7] Reset logic: when state=6 (110), reset to 0. Q2: A 4-bit ripple counter uses FFs with 8ns propagation delay. What's max frequency?
Answer: Total delay = 4 × 8ns = 32ns. Max frequency = 1/(32ns) = 31.25 MHz. For reliable operation, use 80% of this: ~25 MHz. Q3: Show how a shift register converts serial data to parallel.Answer: 4-bit SIPO shift register: serial data enters Q0, each clock shifts right. After 4 clocks, data appears at Q3Q2Q1Q0 in parallel. Used in UART receivers to convert incoming serial bits to parallel byte. Q4: Why do synchronous counters not have glitches?Answer: All flip-flops update simultaneously on the clock edge. Even though the next-state logic settles at different times, the outputs only change on the clock edge when all inputs are stable. Asynchronous counters update sequentially: intermediate states are visible at the outputs (e.g., 7→8 shows 7→6→4→0→8 in binary: 0111→0110→0100→0000→1000).
8. 🔗 Cross-References
- Week 3 - Sequential Circuits: Flip-flop foundations
- Week 6 - Processor Design: CPU registers, program counter
- Week 11 - I/O: Serial communication (UART) Join Discord PreviousSequential CircuitsNextMemory Systems