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Combinational Circuits — MUX, Decoder, Adder, ALU

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Combinational Circuits — MUX, Decoder, Adder, ALU

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Combinational Circuits — MUX, Decoder, Adder, ALU

🎯 Learning Objectives

Design multiplexers and decoders for logic functions
Build half-adder, full-adder, and ripple-carry adder
Explain ALU design using combinational building blocks
Implement any Boolean function using mux or decoder

1. Multiplexers (MUX)

1.1 Intuition

A multiplexer selects one of multiple inputs based on control signals. Like a railroad switch — routes one track among many.

1.2 2:1 MUX


pseudo
S | Y
--|---
0 | A
1 | B
Y = (¬S ∧ A) ∨ (S ∧ B)

1.3 Implementing Functions with MUX

Example: Implement

F = A \oplus B

(XOR) using a 2:1 MUX Use A as select line. When A=0: F = B. When A=1: F = ¬B.


sql
2:1 MUX with select A:
Input 0: B
Input 1: ¬B
Output: A⊕B

1.4 4:1 MUX to implement any 3-variable function

(Diagram) For function

F(A,B,C)

, connect A,B to select lines. Each input is either 0, 1, C, or ¬C.

2. Decoders

2.1 2:4 Decoder

Active-high decoder: exactly one output is 1.


pseudo
A B | Y₀ Y₁ Y₂ Y₃
0 0 |  1  0  0  0
0 1 |  0  1  0  0
1 0 |  0  0  1  0
1 1 |  0  0  0  1

2.2 Implementing Functions with Decoder + OR

Any Boolean function in SOP form can be implemented using a decoder (minterms) + OR gate. Example:

F(A,B,C) = \sum m(0, 2, 5, 7)

Connect A,B,C to 3:8 decoder. Use OR of outputs 0, 2, 5, 7.

3. Adders

3.1 Half Adder

Adds two bits: Sum = A⊕B, Carry = A·B


pseudo
A B | Sum Carry
0 0 |  0    0
0 1 |  1    0
1 0 |  1    0
1 1 |  0    1

3.2 Full Adder

Adds three bits (A + B + CarryIn):


pseudo
Sum = A ⊕ B ⊕ Cin
Cout = (A·B) + (A·Cin) + (B·Cin)

3.3 Ripple-Carry Adder

Four full adders connected in series for 4-bit addition: (Diagram) Propagation delay: Each FA has 2 gate delays. 4-bit adder: 8 gate delays.

4. ALU Design

A simple ALU that can ADD, SUB, AND, OR:

Op	Operation	Implementation
00	AND	A·B
01	OR	A+B
10	ADD	Ripple-carry adder
11	SUB	A + 2's complement of B

(Diagram)

5. 📝 Practice Questions

Q1: Implement a full adder using only 2-input NAND gates.

Answer: First convert to NAND: OR = ¬(¬A · ¬B) using NAND. AND is just NAND + inverter (NAND with both inputs tied). The full adder can be built with about 9 NAND gates. Q2: Design a circuit that compares two 4-bit numbers (A > B).

Answer: Starting from MSB: compare A₃ vs B₃. If A₃=1,B₃=0 → A>B. If equal, compare A₂ vs B₂, etc. Use cascaded comparator stages. Q3: What is the delay of a 32-bit ripple-carry adder?

Answer: Each FA has 2 gate delays for carry propagation. Total = 32 × 2 = 64 gate delays. For faster addition, use carry-lookahead adder (CLA), which computes carries in parallel (≈ 4-5 gate delays regardless of width). Q4: Implement F = A·B + C·D using a single 4:1 MUX.

Answer: Connect A and C to select lines. When A=0,C=0: 0; A=0,C=1: D; A=1,C=0: B; A=1,C=1: B·D. So inputs: I₀=0, I₁=D, I₂=B, I₃=B·D. Q5: What is the advantage of a carry-lookahead adder over a ripple-carry adder?

Answer: Carry-lookahead computes all carries in parallel using generate (Gᵢ = Aᵢ·Bᵢ) and propagate (Pᵢ = Aᵢ⊕Bᵢ) signals. Delay is O(log n) instead of O(n). For 32-bit addition: ripple-carry ≈ 64 gate delays, CLA ≈ 5-8 gate delays.

6. 🔗 Cross-References

Week 1 - Digital Logic: Boolean algebra, gates
Week 3 - Sequential Circuits: Flip-flops for registers
Week 6 - Processor Design: ALU inside CPU Join Discord PreviousBoolean Algebra & K-MapsNextSequential Circuits