Instruction Set Architecture (ISA)
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# Instruction Set Architecture (ISA) ## 🎯 Learning Objectives - Identify MIPS instruction formats (R, I, J) - Explain addressing modes - Encode and decode machine instructions - Compare RISC and CISC philosophies * * * ## 1. MIPS Instruction Formats ### 1.1 R-Type (Register) 31-26 25-21 20-16 15-11 10-6 5-0 opcode...
Instruction Set Architecture (ISA)
🎯 Learning Objectives
- Identify MIPS instruction formats (R, I, J)
- Explain addressing modes
- Encode and decode machine instructions
- Compare RISC and CISC philosophies
1. MIPS Instruction Formats
1.1 R-Type (Register)
| 31-26 | 25-21 | 20-16 | 15-11 | 10-6 | 5-0 |
|---|---|---|---|---|---|
| opcode (6) | rs (5) | rt (5) | rd (5) | shamt (5) | funct (6) |
Example:
add $t0, $s1, $s2 → opcode=0, rs=17(s2), rd=8($t0), shamt=0, funct=32
Encoding: 000000 10001 10010 01000 00000 100000 = 0x023240201.2 I-Type (Immediate)
| 31-26 | 25-21 | 20-16 | 15-0 |
|---|---|---|---|
| opcode (6) | rs (5) | rt (5) | immediate (16) |
Example:
addi $t0, $s1, 100 → opcode=8, rs=17, rt=8, imm=100
Encoding: 001000 10001 01000 0000000001100100 = 0x222800641.3 J-Type (Jump)
| 31-26 | 25-0 |
|---|---|
| opcode (6) | address (26) |
Example:
j 10000 → opcode=2, address=100002. Addressing Modes
| Mode | Example | Effective Address | MIPS Example |
|---|---|---|---|
| Register | add $t0, $t1, $t2 | t2 values | All R-type |
| Immediate | addi $t0, $t1, 100 | $t1 + 100 | addi, andi, ori |
| Base/Displacement | lw $t0, 100($s1) | $s1 + 100 | lw, sw, lb, sb |
| PC-relative | beq $t0, $t1, label | PC + 4 + 4×offset | beq, bne |
| Pseudo-direct | j target | (PC+4)[31:28] ∥ addr × 4 | j, jal |
| Indexed | add $t0, $s1, $s2 | s2 | (via register) |
3. MIPS Core Instruction Set
| Category | Instructions |
|---|---|
| Arithmetic | add, sub, addi, addu, subu |
| Logical | and, or, nor, andi, ori |
| Shift | sll, srl, sra, sllv, srlv |
| Compare | slt, slti, sltu |
| Memory | lw, sw, lb, sb, lh, sh |
| Branch | beq, bne, blez, bgtz, bltz |
| Jump | j, jal, jr |
4. Instruction Encoding Example
Assembly:
lw $t0, 32($sp)| Field | opcode | rs | rt | immediate |
|---|---|---|---|---|
| Value | 35 (lw) | 29 ($sp) | 8 ($t0) | 32 |
| Binary | 100011 | 11101 | 01000 | 0000000000100000 |
Hex: 0x8FA80020
5. Common Pitfalls
Pitfall: MIPS Branch Addressing
The mistake: Forgetting that branch offsets are relative to PC+4 and multiplied by 4.
Correct approach: Target = PC + 4 + (offset × 4). The offset is number of instructions to skip (not bytes). Maximum forward/backward range: ±128KB.
6. Key Concepts Reference
| Concept | Description |
|---|---|
| R-type | Register operands (3 registers) |
| I-type | Immediate operand (16-bit) |
| J-type | Jump target (26-bit address) |
| PC-relative | Branch target = PC + offset |
| Base+offset | Memory address = register + constant |
| Endianness | Byte order in memory |
| Word alignment | 32-bit words at addresses divisible by 4 |
7. 📝 Practice Questions
Q1: Encodesub $t3, $s0, $s7in MIPS.Answer: R-type: opcode=0, rs=16(s7), rd=11($t3), shamt=0, funct=34(sub). Binary: 000000 10000 10111 01011 00000 100010 = 0x02175822 Q2: Decode 0xAD550004.Answer: Binary: 101011 01010 10101 0000000000000100. opcode=43=sw, rs=10(s5), imm=4. Assembly:sw $s5, 4($t2)Q3: Forbeq $t0, $t1, loopwhere loop is at PC-24, what's the offset?Answer: Target = PC + 4 + 4×offset. -24 = 4 + 4×offset → offset = -7. In 16-bit: 0xFFF9 (2's complement). Q4: How many MIPS registers are there and why?Answer: 32 general-purpose registers (5-bit addressing). MIPS is a RISC architecture — more registers require more bits in instruction encoding. 32 registers balances: (1) enough for variables, (2) reasonable instruction size (32-bit), (3) 5-bit register fields leave room for opcode, funct, immediate in 32-bit words.
8. 🔗 Cross-References
- Week 6 - Processor Design: Datapath for instructions
- Week 9 - Pipelining: Hazards from different instruction types
- Week 12 - RISC vs CISC: ISA design philosophies Join Discord PreviousComputer ArithmeticNextPipelining