Computer Arithmetic

🎯 Learning Objectives

• Design ripple-carry and carry-lookahead adders
• Implement signed addition/subtraction using 2's complement
• Explain Booth's multiplication algorithm
• Represent numbers using IEEE 754 floating-point

1. Binary Addition

1.1 Half Adder

1.2 Full Adder

1.3 Ripple-Carry Adder (4-bit)

2. Carry-Lookahead Adder (CLA)

• $G_i = A_i \land B_i$ (generate carry)
• $P_i = A_i \lor B_i$ (propagate carry)
• $C_{i+1} = G_i \lor (P_i \land C_i)$ For 4-bit CLA:
• $C_1 = G_0 \lor (P_0 \land C_0)$
• $C_2 = G_1 \lor (P_1 \land G_0) \lor (P_1 \land P_0 \land C_0)$
• $C_3 = G_2 \lor (P_2 \land G_1) \lor (P_2 \land P_1 \land G_0) \lor (P_2 \land P_1 \land P_0 \land C_0)$ Delay: 4 gate delays regardless of width (for 4-bit blocks).

3. Subtraction using 2's Complement

• 7 = 0111
• 3 = 0011 → invert: 1100 → +1: 1101 (-3 in 2's comp)
• 0111 + 1101 = 10100 → discard overflow → 0100 = 4 ✓

4. Booth's Multiplication Algorithm

1. Examine bits of multiplier: 01 = +multiplicand, 10 = -multiplicand, 00/11 = no op
2. Shift partial product right after each step Example: 3 × 2 = 6 (3-bit)

• (0,0): no op, shift
• (1,0): subtract, shift
• (0,1): add, shift Actually let me use a simpler approach. 3 × 2:
• 3 (0011) × 2 (0010) Standard binary multiplication:

pseudo
   0011  (3)
 × 0010  (2)
 -------
   0000  (3 × 0)
  0011   (3 × 1, shift)
 -------
  000110 (6)

5. IEEE 754 Floating Point

• 1 bit sign | 8 bits exponent | 23 bits mantissa Example: Represent 5.75
• Binary: 101.11 = 1.0111 × 2²
• Sign: 0 (positive)
• Exponent: 2 + 127 = 129 = 10000001
• Mantissa: 01110000000000000000000
• Result: 0 10000001 01110000000000000000000

6. Common Pitfalls

Pitfall: Overflow Detection

7. Key Concepts Reference

8. 📝 Practice Questions

Q1: Add 0101 (5) + 0011 (3) using ripple-carry.

Answer: Bit 0: 1+1=0, carry=1 Bit 1: 0+1+1=0, carry=1 Bit 2: 1+0+1=0, carry=1 Bit 3: 0+0+1=1, carry=0 Result: 1000 (8). Correct. Q2: Why does CLA become complex beyond 4 bits?

Answer: The carry equations grow quickly: C₄ requires a 5-input OR of 5 AND terms. For 64-bit CLA, the equations would be enormous. Solution: hierarchical CLA (4-bit blocks with block generate/propagate). Group 4×4-bit CLAs into 16-bit CLA, then 4×16-bit into 64-bit. Q3: Compute -5 + 3 in 4-bit 2's complement.

Answer: -5 = 1011, 3 = 0011. 1011 + 0011 = 1110 = -2. Check: -5 + 3 = -2 ✓. No overflow (Carry_in = Carry_out = 1 for sign bit). Q4: IEEE 754: What decimal is 0 10000010 10100000000000000000000?

Answer: Sign = 0 (+). Exponent = 10000010 = 130, subtract 127 = 3. Mantissa = 1.101 = 1.625. Value = 1.625 × 2³ = 13.0.

9. 🔗 Cross-References

• Week 2 - Combinational Circuits: Adder circuits
• Week 6 - Processor Design: ALU in processor
• Week 8 - ISA: Arithmetic instructions Join Discord PreviousProcessor DesignNextISA