Processor Design — Datapath, Control Unit, Instruction Execution
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# Processor Design — Datapath, Control Unit, Instruction Execution ## 🎯 Learning Objectives - Identify components of a CPU datapath - Design a simple control unit - Trace instruction execution through datapath stages - Explain the fetch-decode-execute cycle * * * ## 1. Basic CPU Architecture *(Diagram)* ### 1.1 Dat...
Processor Design — Datapath, Control Unit, Instruction Execution
🎯 Learning Objectives
- Identify components of a CPU datapath
- Design a simple control unit
- Trace instruction execution through datapath stages
- Explain the fetch-decode-execute cycle
1. Basic CPU Architecture
(Diagram)
1.1 Datapath Components
| Component | Function |
|---|---|
| Program Counter (PC) | Address of current instruction |
| Instruction Memory | Stores program (could be ROM) |
| Register File | General-purpose registers (e.g., 32 × 32-bit) |
| ALU | Performs arithmetic/logic operations |
| Data Memory | RAM for data storage |
2. Instruction Execution Cycle
2.1 Fetch-Decode-Execute
(Diagram)
2.2 R-Type Instructions (e.g., ADD Rd, Rs, Rt)
| Stage | Action |
|---|---|
| IF | IR ← M[PC]; PC ← PC + 4 |
| ID | Read Rs, Rt from register file |
| EX | ALUout ← Rs op Rt |
| MEM | (no memory access) |
| WB | Rd ← ALUout |
2.3 I-Type Instructions (e.g., LW Rt, offset(Rs))
| Stage | Action |
|---|---|
| IF | IR ← M[PC]; PC ← PC + 4 |
| ID | Read Rs from register file; sign-extend offset |
| EX | ALUout ← Rs + offset |
| MEM | Data ← M[ALUout] |
| WB | Rt ← Data |
3. Control Unit
3.1 Control Signals
| Signal | Effect | R-Format | LW | SW | Branch |
|---|---|---|---|---|---|
| RegDst | Write register: rd(1)/rt(0) | 1 | 0 | X | X |
| ALUSrc | ALU input: register(0)/immediate(1) | 0 | 1 | 1 | 0 |
| MemtoReg | Write data: ALU(0)/Memory(1) | 0 | 1 | X | X |
| MemRead | Read data memory | 0 | 1 | 0 | 0 |
| MemWrite | Write data memory | 0 | 0 | 1 | 0 |
| RegWrite | Write register file | 1 | 1 | 0 | 0 |
| Branch | Branch instruction | 0 | 0 | 0 | 1 |
4. 📝 Practice Questions
Q1: What is the role of the Program Counter?Answer: The PC holds the address of the next instruction to execute. It's incremented by 4 (for 32-bit instructions) during the fetch stage. For branches and jumps, it's updated with the target address. Q2: How does the control unit generate signals from the instruction opcode?Answer: The opcode bits of the instruction are input to combinational logic (or a decoder) that sets each control signal to 0 or 1 based on the instruction type. For example, if opcode = 0 (R-type), RegDst=1, ALUSrc=0, RegWrite=1. Q3: Why is the register file a critical component in CPU design?Answer: The register file provides fast access to operands (typically 32 registers, each 32-bit). It needs two read ports and one write port to support instructions like ADD which read two source registers and write one destination register in a single cycle. Q4: What is the difference between a single-cycle and multi-cycle processor?Answer: Single-cycle executes each instruction in one clock cycle (cycle time = longest instruction = LW). Multi-cycle uses multiple shorter cycles per instruction, running different stages each cycle — better average performance but more complex control. Q5: How does the ALU know which operation to perform?Answer: For R-type instructions, the funct field (bits 5:0) selects the ALU operation. The ALU control logic decodes the funct field (in combination with ALUOp from the main control unit) to generate ALU control signals (e.g., 0010 for ADD, 0110 for SUB).
5. 🔗 Cross-References
- Week 2 - Combinational Circuits: ALU components
- Week 3 - Sequential Circuits: Registers, PC
- Week 8 - ISA: Instruction formats, addressing modes
- BSCS4022 (OS): CPU modes, interrupt handling Join Discord PreviousMemory SystemsNextComputer Arithmetic