Memory Systems — RAM, ROM, Decoder-Based Memory
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# Memory Systems — RAM, ROM, Decoder-Based Memory ## 🎯 Learning Objectives - Distinguish SRAM vs. DRAM vs.
Memory Systems — RAM, ROM, Decoder-Based Memory
🎯 Learning Objectives
- Distinguish SRAM vs. DRAM vs. ROM
- Design decoder-based memory addressing
- Explain memory hierarchy (cache, main memory, disk)
- Analyze memory access times and hit rates
1. Memory Types
| Type | Volatile? | Speed | Density | Cost/bit | Use |
|---|---|---|---|---|---|
| SRAM | Yes | Fastest (1-10ns) | Low (6T/cell) | High | Cache |
| DRAM | Yes | Fast (10-50ns) | High (1T+1C) | Low | Main memory |
| ROM | No | Fast | Medium | Medium | Firmware, BIOS |
| Flash | No | Medium (read), Slow (write) | Very high | Very low | Storage |
2. Decoder-Based Memory
2.1 Address Decoding
(Diagram)
1024 × 8-bit memory: 10 address lines (A0-A9), 8 data lines (D0-D7).
Address map:
| Address (Binary) | Address (Hex) | Word Selected |
|---|---|---|
| 00 0000 0000 | 000 | Word 0 |
| 00 0000 0001 | 001 | Word 1 |
| ... | ... | ... |
| 11 1111 1111 | 3FF | Word 1023 |
2.2 Chip Select
For larger memories, use chip select (CS) to enable specific memory chips:
(Diagram)
3. Memory Hierarchy
| Level | Size | Access Time | Managed By |
|---|---|---|---|
| Registers | 100s bytes | 0.3ns | Compiler |
| L1 Cache | 32-64KB | 1ns | Hardware |
| L2 Cache | 256-512KB | 3-5ns | Hardware |
| L3 Cache | 4-32MB | 10-15ns | Hardware |
| Main Memory | 8-64GB | 50-100ns | OS |
| SSD | 256GB-2TB | 10-100μs | OS/User |
| HDD | 1-10TB | 5-15ms | OS/User |
4. Common Pitfalls
Pitfall: Confusing Byte Addressability with Word Size
The mistake: Assuming 32-bit address space means 32-bit words.
Correct approach: 32-bit address space = 2^32 bytes = 4GB addressable. Whether the processor fetches 8, 16, 32, or 64 bits at a time is a different design choice.
5. Key Concepts Reference
| Concept | Description |
|---|---|
| SRAM | Static RAM (bistable latch) |
| DRAM | Dynamic RAM (capacitor, needs refresh) |
| Address decoder | Converts address to chip/word select |
| Memory map | Assignment of addresses to memory regions |
| Chip select | Enables specific memory chip |
| Endianness | Byte order (little-endian vs big-endian) |
6. 📝 Practice Questions
Q1: How many address lines for a 64KB memory with 8-bit words?Answer: 64KB = 64 × 1024 = 65536 bytes. Need log₂(65536) = 16 address lines (A0-A15). Q2: A system has 16-bit address bus with 8-bit data. Memory chips are 2KB each. How many chips needed?Answer: Total addressable = 2^16 = 64KB. Each chip = 2KB. Chips needed = 64/2 = 32. Address lines per chip: 2KB = 2048, need 11 address lines. Remaining 5 address lines used for chip select (32 chips). Q3: Why does DRAM need refresh while SRAM doesn't?Answer: DRAM stores charge on a capacitor, which leaks over time (typically 64ms). SRAM uses a bistable latch (6 transistors) that maintains state as long as power is applied. DRAM must read and rewrite every row periodically (refresh cycle), consuming ~1% of memory bandwidth. Q4: Calculate effective access time: L1 hit rate = 95%, L2 hit rate = 90%, L1 time = 1ns, L2 time = 10ns, main memory = 100ns.Answer: Effective time = 0.95 × 1ns + 0.05 × (0.90 × 10ns + 0.10 × (10ns + 100ns)) = 0.95 + 0.05 × (9 + 11) = 0.95 + 0.05 × 20 = 0.95 + 1.0 = 1.95ns. Without cache: 100ns. Improvement: 50× faster.
7. 🔗 Cross-References
- Week 10 - Cache: Cache organization
- Week 6 - Processor Design: Memory access in CPU
- BSCS4022 (OS): Memory management, virtual memory Join Discord PreviousCounters & RegistersNextProcessor Design